In the design of integrated circuits, such as memory circuits, power consumption is an issue that receives much attention. In a memory circuit, a memory array typically includes a plurality of memory cells. With reduced physical size of integrated circuit components in submicron technologies, and the desire to reduce operating power, transistors with a reduced threshold voltage are used in memory cells. Consequently, leakage current becomes a dominant portion of static power consumption.
In power conscious applications it is sometimes desirable to reduce the standby leakage current of a random access memory, such as SRAM. This can be done by turning off power to the SRAM. However, this will cause the SRAM to lose the data stored in it. SRAM is a type of semiconductor memory that retains its contents as long as power remains applied. Therefore, in low power consumption operating modes, such as standby, the SRAM data must be retained while minimizing the power consumption due to leakage.
Some known solutions address the reduction of leakage currents. Transistor stacks, also known as self-reverse bias, use a technique that gives a large reduction in leakage current, but requires a large area increase in the memory cell. Simple gated-ground, or virtual ground, techniques have poor control over the voltage on the virtual ground node. A dynamic threshold voltage technique, also known as body biasing, requires a more complicated fabrication process known as a triple well process.
Prior solutions appear to have had very poor control over the virtual ground voltage, so the reliability of data retention was not quantifiable. Most solutions did not have any mechanism for limiting the virtual ground voltage based on any circuit parameter that could affect the stability of the memory cells.
It is, therefore, desirable to provide an approach that reduces leakage current while maintaining data integrity, without a significant burden in complexity or cost.